1. Field
The described embodiments relate to clock-control circuits. More specifically, the described embodiments relate to an integrated pulse-control and enable latch.
2. Related Art
Many integrated circuits use a clock signal for timing purposes. For example, integrated circuits can include flip-flops, latches, domino circuits, memories, or other types of circuits that are controlled or timed using a clock signal. In some integrated circuits, the clock signal is a pulsed signal. For example, some integrated circuits can include pulse latches, memory circuits such as synchronous random-access memories (SRAMs), or other circuits that are controlled or timed using pulsed signals.
Within an integrated circuit, clock signals are often distributed to large numbers of circuit elements. Consequently, many integrated circuits include dedicated circuits for distributing the clock signal. For example, FIG. 1 presents an exemplary clock header 100 used to distribute a clock signal in an integrated circuit. Clock header 100 takes clock input 102 and clock enable signal 104 as inputs and outputs clock output signal 106. When asserted (i.e., a logical “1”), clock enable signal 104 enables clock input 102 to propagate through clock header 100 to form clock output signal 106. Clock output signal 106 can then be used as a clock signal for other circuits (not shown).
For clock header 100, if clock enable signal 104 transitions at an incorrect time, it can corrupt clock output signal 106. More specifically, if an improperly timed rising or falling edge on clock enable signal 104 occurs during the high phase of clock input 102, it can cause the high phase of clock output signal 106 to be shorter than an expected duration. The corrupted high phase of clock output signal 106 can, in turn, cause serious errors in the circuits that use clock output signal 106 as a timing signal.
In order to avoid errors caused by mistimed transitions in the clock enable signal, some systems use a clock enable control to generate the clock enable signal. For example, FIG. 2 presents an exemplary clock enable control latch 200. Clock enable control latch 200 takes one or more enable signals (e.g., global power clock enable (GPCE) 202, power clock enable (PCE) 204, and power clock enable override (PCE_OV) 206) and a clock input 208 as inputs and outputs a clock enable signal 210. Within clock enable control latch 200, the latch that is formed by the back-to-back pair of the inverter that drives clock enable signal 210 and the tri-state inverter driven by clock enable signal 210 is transparent during the low phase of clock input 208, but becomes non-transparent and captures the value on the enable signals as clock input 208 rises, thereby setting the clock enable signal 210 at the captured value for the duration of the high phase of clock input 208.
FIG. 3 presents an exemplary clock generation circuit 300 that uses clock enable control latch 200 and clock header 100 to generate clock output signal 310. As can be seen in FIG. 3, clock enable control latch 200 provides a clock enable signal to the NAND gate in clock header 100. Because the clock enable signal generated by clock enable control latch 200 is prevented from transitioning during the high phase of clock input 308, clock generation circuit 300 can output clock output signal 310 without the above-described errors in clock output signal 310 caused by mistimed transitions in the enable signal.
Note that, in the configuration shown in FIG. 3, if the enable output of clock enable control latch 200 is asserted, clock input 308 is passed through clock generation circuit 300 to clock output signal 310 with no changes to the waveform of clock input 308 (i.e., clock output signal 310 has the same duty-cycle as clock input 308).
Unlike the circuit shown in FIG. 3, which can be used for integrated circuits that use a full duty-cycle clock signal, integrated circuits that use a pulsed clock can require an additional clock pulse control circuit that is used to control the length of the pulses in the clock signal. For example, FIG. 4 presents an exemplary clock pulse control circuit 400. Clock pulse control circuit 400 takes disable signal 404 and clock input 402 as inputs and outputs clock control output signal 406. If disable signal 404 is deasserted (i.e., a logical “0”), a falling edge on clock input 402 feeds through clock pulse control circuit 400 to cause a rising edge on clock control output signal 406. Clock control output signal 406 is then used to control a clock waveform that feeds back through a clock path (see, e.g., clock header 100 in FIG. 5) to form a rising edge on feedback signal 408, which pulls clock control output signal 406 low, ending the rising pulse on clock control output signal 406.
When coupled to the clock enable signal 104 input of a clock header 100, clock pulse control circuit 400 can control the pulse length in a pulsed clock. However, like the above-described clock circuits, glitches can occur on the clock signal output from clock header 100 if disable signal 404 is not prevented from switching at an incorrect time. A clock enable control latch 200 can be used to prevent the enable from switching incorrectly. However, clock enable control latch 200 provides an active-high (i.e., asserted) clock enable signal 210, while clock pulse control circuit 400 requires an active-low (i.e., deasserted) disable signal 404. Thus, if clock pulse control circuit 400 is to be used with clock enable control latch 200, either the enable signals must be inverted, or another modification must be made to clock enable control latch 200 to provide disable signal 404 in the correct logical state.
FIG. 5 presents an exemplary pulse clock generation circuit 500 that uses clock enable control latch 200, clock pulse control circuit 400, and clock header 100 to generate a pulsed clock output signal 502. As can be seen in FIG. 5, clock enable control latch 200 provides the disable signal to clock pulse control circuit 400 which, in turn, provides a control pulse to clock header 100. Clock circuit 500 therefore outputs a pulsed clock output signal 502 that is free from glitches caused by mistimed transitions in the enable signals. As described above, the enable signals (i.e., GPCE 506, PCE 508, and PCE_OV 510) to clock enable control latch 200 in this configuration must be logically inverted in comparison to the enable signals to clock enable control latch 200 in the configuration shown in FIG. 3.
Because pulse clock generation circuit 500 in the configuration shown in FIG. 5 requires the enable signals to clock enable control latch 200 to be logically inverted with respect to the enable signals used by clock enable control latch 200 as shown in the configuration in FIG. 3, a circuit designer who wishes to change a normal (i.e., full duty-cycle) clock to a pulsed clock by switching these circuits must also provide inverted enable signals and add a clock pulse control circuit 400. Hence, due to area constraints, timing constraints, and other considerations, swapping a full duty-cycle clock to a pulsed clock can be difficult. This can limit the designer's ability to replace full duty-cycle clocks with higher-performance pulsed clocks.